C8051F019-GQ Silicon Laboratories Inc, C8051F019-GQ Datasheet - Page 110
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C8051F019-GQ
Manufacturer Part Number
C8051F019-GQ
Description
IC 8051 MCU 16K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F018r
Specifications of C8051F019-GQ
Program Memory Type
FLASH
Program Memory Size
16KB (16K x 8)
Package / Case
48-TQFP, 48-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
16
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
16
Number Of Timers
4
Operating Supply Voltage
2.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
No. Of I/o's
16
Ram Memory Size
1.25KB
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1198
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F019-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F019-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
15.4.
The SPI is accessed and controlled through four special function registers in the system controller: SPI0CN Control
Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four
special function registers related to the operation of the SPI Bus are described in the following section.
Bit7:
Bit6:
Bits5-3: BC2-BC0: SPI Bit Count.
Bits2-0: SPIFRS2-SPIFRS0: SPI Frame Size.
.
CKPHA
R/W
Bit7
SPI Special Function Registers
This bit controls the SPI clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
This bit controls the SPI clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
Indicates which of the up to 8 bits of the SPI word have been transmitted.
These three bits determine the number of bits to shift in/out of the SPI shift register
during a data transfer in master mode. They are ignored in slave mode.
CKPHA: SPI Clock Phase.
CKPOL: SPI Clock Polarity.
CKPOL
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R/W
Bit6
BC2-BC0
SPIFRS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Figure 15.5. SPI0CFG: SPI Configuration Register
BC2
Bit5
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BC1
Bit4
Bits Shifted
Bit Transmitted
R
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7 (MSB)
1
2
3
4
5
6
7
8
Rev. 1.2
BC0
Bit3
R
SPIFRS2
R/W
Bit2
SPIFRS1
R/W
Bit1
C8051F018
C8051F019
SPIFRS0
R/W
Bit0
SFR Address:
Reset Value
00000111
0x9A
110