MC68HC908LK24CFU Freescale Semiconductor, MC68HC908LK24CFU Datasheet - Page 293
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MC68HC908LK24CFU
Manufacturer Part Number
MC68HC908LK24CFU
Description
IC MCU 24K FLASH 8MHZ SPI 64-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC68HC908LK24CFU
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LK24CFU
Manufacturer:
FREESCALE Semiconductor
Quantity:
489
Company:
Part Number:
MC68HC908LK24CFU
Manufacturer:
Freescale Semiconductor
Quantity:
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14.6 Transmission Formats
14.6.1 Clock Phase and Polarity Controls
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
NOTE:
When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise,
the byte already in the slave shift register shifts out on the MISO pin.
Data written to the slave shift register during a transmission remains in
a buffer until the end of the transmission.
When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. (See
SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.
During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock synchronizes
shifting and sampling on the two serial data lines. A slave select line
allows selection of an individual slave SPI device; slave devices that are
not selected do not interfere with SPI bus activities. On a master SPI
device, the slave select line can optionally be used to indicate multiple-
master bus contention.
Software can select any of four combinations of serial clock (SPSCK)
phase and polarity using two bits in the SPI control register (SPCR). The
clock polarity is specified by the CPOL control bit, which selects an
active high or low clock and has no significant effect on the transmission
format.
Serial Peripheral Interface Module (SPI)
14.6 Transmission
Serial Peripheral Interface Module (SPI)
Formats.)
Transmission Formats
Data Sheet
293
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