MC9S12XEQ512CAG Freescale Semiconductor, MC9S12XEQ512CAG Datasheet - Page 636

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MC9S12XEQ512CAG

Manufacturer Part Number
MC9S12XEQ512CAG
Description
MCU 16BIT 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12XEQ512CAG

Core Processor
HCS12X
Core Size
16-Bit
Speed
50MHz
Connectivity
CAN, EBI/EMI, I²C, IrDA, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XE
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
119
Number Of Timers
25
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.3.3.1.1
636
Module Base + 0x00X0
Module Base + 0x00X1
ID[28:21]
ID[20:18]
ID[17:15]
Field
Field
SRR
IDE
7-0
7-5
2-0
4
3
Reset:
Reset:
W
W
R
R
Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
Substitute Remote Request — This fixed recessive bit is used only in extended format. It must be set to 1 by
the user for transmission buffers and is stored as received on the CAN bus for receive buffers.
ID Extended — This flag indicates whether the extended or standard identifier format is applied in this buffer. In
the case of a receive buffer, the flag is set as received and indicates to the CPU how to process the buffer
identifier registers. In the case of a transmit buffer, the flag indicates to the MSCAN what type of identifier to send.
0 Standard format (11 bit)
1 Extended format (29 bit)
Extended Format Identifier — The identifiers consist of 29 bits (ID[28:0]) for the extended format. ID28 is the
most significant bit and is transmitted first on the CAN bus during the arbitration procedure. The priority of an
identifier is defined to be highest for the smallest binary number.
IDR0–IDR3 for Extended Identifier Mapping
ID28
ID20
7
x
Figure 16-26. Identifier Register 0 (IDR0) — Extended Identifier Mapping
7
x
Figure 16-27. Identifier Register 1 (IDR1) — Extended Identifier Mapping
Table 16-27. IDR0 Register Field Descriptions — Extended
Table 16-28. IDR1 Register Field Descriptions — Extended
ID27
ID19
6
x
6
x
MC9S12XE-Family Reference Manual , Rev. 1.23
ID26
ID18
5
x
5
x
SRR (=1)
ID25
4
x
4
x
Description
Description
IDE (=1)
ID24
x
x
3
3
ID23
ID17
2
x
2
x
Freescale Semiconductor
ID22
ID16
x
x
1
1
ID21
ID15
0
x
0
x

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