MC9S12XEQ512CAG Freescale Semiconductor, MC9S12XEQ512CAG Datasheet - Page 248

• Manufacturer Part Number: MC9S12XEQ512CAG
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 External Bus Interface (S12XEBIV4)
1. All inputs are capable of reducing input threshold level
2. Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
3. Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
248
RE
ADDR[22:20]
ACC[2:0]
ADDR[19:16]
IQSTAT[3:0]
ADDR[15:1]
IVD[15:1]
ADDR0
IVD0
UDS
LSTRB
LDS
RW
WE
CS[3:0]
DATA[15:8]
DATA[7:0]
EWAIT
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
time slot (in modes where applicable).
depending on configuration and reset state.
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Signal
I
(1)
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
/O
(F)unction
EBI Signal
—
—
—
—
—
—
—
—
—
—
Multiplex
T
T
T
T
(T)ime
Table 5-2. External System Signals Associated with XEBI
(2)
—
—
—
—
—
—
—
—
—
—
—
F
F
F
(3)
MC9S12XE-Family Reference Manual , Rev. 1.23
Read Enable, indicates external read access
External address
Access source
External address
Instruction Queue Status
External address
Internal visibility read data
External address
Internal visibility read data
Upper Data Select, indicates external access
to the high byte DATA[15:8]
Low Strobe, indicates valid data on DATA[7:0]
Lower Data Select, indicates external access
to the low byte DATA[7:0]
Read/Write, indicates the direction of internal
data transfers
Write Enable, indicates external write access
Chip select
Bidirectional data (even address)
Bidirectional data (odd address)
External control for external bus access
stretches (adding wait states)
Description
NS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
SS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Available in Modes
Freescale Semiconductor
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NX
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ES
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EX
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST
No
No
No
No
No
No