MC9S12C32CFAE16 Freescale Semiconductor, MC9S12C32CFAE16 Datasheet - Page 217

• Manufacturer Part Number: MC9S12C32CFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32CFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 16MHz
• Interface Type: CAN/SCI/SPI
• Total Internal Ram Size: 2KB
• # I/os (max): 31
• Number Of Timers - General Purpose: 8
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/2.97V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Package: 48LQFP
• Family Name: HCS12
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 2.5|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 31
• Number Of Timers: 8
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

7.4.2.5.4
In the event-only B trigger mode, if the match condition for B is met, the B flag in DBGSC is set and a
trigger occurs. The event-only B trigger mode is considered a begin-trigger type and the BEGIN bit in
DBGC1 is ignored. Event-only B is incompatible with instruction tagging (TRGSEL = 1), and thus the
value of TRGSEL is ignored. Please refer to
This trigger mode is incompatible with the detail capture mode so the detail capture mode will have
priority. TRGSEL and BEGIN will not be ignored and this trigger mode will behave as if it were “B only”.
7.4.2.5.5
In the A then event-only B trigger mode, the match condition for A must be met before the match condition
for B is compared, after the A match has occurred, a trigger occurs each time B matches. When the match
condition for A or B is met, the corresponding flag in DBGSC is set. The A then event-only B trigger mode
is considered a begin-trigger type and BEGIN in DBGC1 is ignored. TRGSEL in DBGC1 applies only to
the match condition for A. Please refer to
This trigger mode is incompatible with the detail capture mode so the detail capture mode will have
priority. TRGSEL and BEGIN will not be ignored and this trigger mode will be the same as A then B.
7.4.2.5.6
In the A and B trigger mode, comparator A compares to the address bus and comparator B compares to
the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle,
both the A and B flags in the DBGSC register are set and a trigger occurs.
If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and
comparator B matches are ignored. If TRGSEL = 0, full-word data matches on an odd address boundary
(misaligned access) do not work unless the access is to a RAM that manages misaligned accesses in a
single clock cycle (which is typical of RAM modules used in HCS12 MCUs).
7.4.2.5.7
In the A and not B trigger mode, comparator A compares to the address bus and comparator B compares
to the data bus. In the A and not B trigger mode, if the match condition for A and not B happen on the same
bus cycle, both the A and B flags in DBGSC are set and a trigger occurs.
If TRGSEL = 1, only matches from comparator A are used to determine if the trigger condition is met and
comparator B matches are ignored. As described in
data compares on misaligned accesses will not match expected data (and thus will cause a trigger in this
mode) unless the access is to a RAM that manages misaligned accesses in a single clock cycle.
Freescale Semiconductor
least six addresses higher than address A (or B is lower than A) and there
are not changes of flow to put these in the queue at the same time, then this
operation should trigger properly.
Event-Only B (Store Data)
A then Event-Only B (Store Data)
A and B (Full Mode)
A and Not B (Full Mode)
MC9S12C-Family / MC9S12GC-Family
Section 7.4.2.7, “Storage
Section 7.4.2.7, “Storage
Rev 01.24
Section 7.4.2.5.6, “A and B (Full
Chapter 7 Debug Module (DBGV1) Block Description
Memory,” for more information.
Memory,” for more information.
Mode),” full-word
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