MCF52223CAF80 Freescale Semiconductor, MCF52223CAF80 Datasheet - Page 37

• Manufacturer Part Number: MCF52223CAF80
• Description: IC MCU 256K FLASH 80MHZ 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF5222xr

Specifications of MCF52223CAF80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF522x
• Core: ColdFire V2
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C/QSPI/UART/USB
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 10
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52221DEMO, M52223EVB
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 12-bit
• For Use With: M52223EVB - BOARD EVAL FOR MCF52223
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
Figure 8
2.12
Table 35
37
V
Name
V
V
t
V
f
RES
DNL
t
t
C
R
ADPU
t
ADIC
REFH
INL
INL
REFL
ADIN
REC
ADC
ADS
DDA
ADI
AD
shows timing for the values in
lists specifications for the analog-to-digital converter.
SDA
SCL
1
2
3
Analog-to-Digital Converter (ADC) Parameters
Low reference voltage
High reference voltage
ADC analog supply voltage
Input voltages
Resolution
Integral non-linearity (full input signal range)
Integral non-linearity (10% to 90% input signal range)
Differential non-linearity
ADC internal clock
Conversion range
ADC power-up time
Recovery from auto standby
Conversion time
Sample time
Input capacitance
Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the
maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
interface is designed to scale the actual data transition time to move it to the middle of the SCL low
period. The actual position is affected by the prescale and division values programmed into the IFDR;
however, the numbers given in
Because SCL and SDA are open-collector-type outputs, which the processor can only actively drive
low, the time SCL or SDA take to reach a high level depends on external signal capacitance and pull-up
resistor values.
Specified at a nominal 50-pF load.
I1
Monotonicity
5
I2
Characteristic
Table 33
I4
MCF52223 ColdFire Microcontroller, Rev. 3
Figure 8. I
Table 34
Table 35. ADC Parameters
and
Table
I6
are minimum values.
2
C Input/Output Timings
2
34.
I7
4
V
V
V
Min
V
REFL
3.0
REFL
0.1
REFL
12
—
—
—
—
—
—
—
—
SS
1
I8
–1 < DNL < 1
See
Typical
2.5
2.5
Figure 9
3.3
—
—
—
—
—
—
GUARANTEED
6
0
6
1
I5
I3
Table
Freescale Semiconductor
34. The I
V
V
V
V
Max
<1
REFH
REFH
REFH
3.6
5.0
12
3
3
13
DDA
—
—
—
1
I9
2
C
t
t
t
t
AIC
AIC
AIC
AIC
LSB
MHz
Unit
LSB
LSB
Bits
cycles
pF
cycles
cycles
cycles
V
V
V
V
V
3
6