R5F2L3A8ANFP#U1 Renesas Electronics America, R5F2L3A8ANFP#U1 Datasheet - Page 606

• Manufacturer Part Number: R5F2L3A8ANFP#U1
• Description: MCU 1KB FLASH 64K ROM 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/Lx/3AAr

Specifications of R5F2L3A8ANFP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: LCD, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 88
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 20x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

R8C/L35A Group, R8C/L36A Group, R8C/L38A Group, R8C/L3AA Group,
R8C/L35B Group, R8C/L36B Group, R8C/L38B Group, R8C/L3AB Group
REJ09B0441-0100 Rev.1.00
Page 569 of 802
Figure 26.9
Note:
(1)
(2)
(3)
(4)
(5)
(6)
1. Write 0 after reading 1 to set the TEND bit to 0.
Read receive data from the SSRDR register
Write transmit data to the SSTDR register
Communication Mode)
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
SSSR register
SSER register
Read the TDRE bit in the SSSR register
Read the RDRF bit in the SSSR register
Read the TEND bit in the SSSR register
No
Initialization
TDRE = 1?
RDRF = 1?
transmission
TEND = 1?
continues?
Oct 30, 2009
Start
Data
End
TEND bit
RE bit
TE bit
Yes
Yes
No
Yes
0
0
0
No
No
Yes
(1)
26. Synchronous Serial Communication Unit (SSU)
(2) Confirm that the RDRF bit is set to 1.
(3) Determine whether data transmission continues.
(4) When the data transmission is completed,
(5) Set the TEND bit to 0, and bits RE and TE
(6) in the SSER register to 0 before ending
(1) After reading the SSSR register and confirming
If the RDRF bit is set to 1, read receive data in
the SSRDR register. When the SSRDR register
is read, the RDRF bit is automatically set to 0.
the TEND bit in the SSSR register is set to 1.
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
transmit/receive mode.