MC908AP32ACFBE Freescale Semiconductor, MC908AP32ACFBE Datasheet - Page 172
![IC MCU 32K FLASH 8MHZ 44-QFP](/photos/39/61/396111/4243290_sml.jpg)
MC908AP32ACFBE
Manufacturer Part Number
MC908AP32ACFBE
Description
IC MCU 32K FLASH 8MHZ 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908AP16ACFBER.pdf
(316 pages)
Specifications of MC908AP32ACFBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SCI, SPI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
Controller Family/series
HC08
No. Of I/o's
32
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI, SPI
Rohs Compliant
Yes
Processor Series
HC08AP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908AP64E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Manufacturer
Quantity
Price
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MC908AP32ACFBE
Manufacturer:
FREESCALE
Quantity:
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MC908AP32ACFBE
Manufacturer:
Freescale Semiconductor
Quantity:
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MC908AP32ACFBE
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Manufacturer:
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Serial Communications Interface Module (SCI)
FE — Receiver Framing Error Bit
PE — Receiver Parity Error Bit
172
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an SCI error
CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.
This clearable, read-only bit is set when the SCI detects a parity error in incoming data. PE generates
an SCI error CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Framing error detected
0 = No framing error detected
1 = Parity error detected
0 = No parity error detected
BYTE 1
BYTE 1
READ SCS1
READ SCDR
SCRF = 1
BYTE 1
OR = 0
Figure 11-13. Flag Clearing Sequence
MC68HC908AP A-Family Data Sheet, Rev. 3
READ SCDR
READ SCS1
DELAYED FLAG CLEARING SEQUENCE
NORMAL FLAG CLEARING SEQUENCE
BYTE 2
BYTE 2
SCRF = 1
BYTE 1
OR = 0
READ SCDR
READ SCS1
SCRF = 1
BYTE 2
OR = 0
BYTE 3
BYTE 3
READ SCDR
READ SCDR
READ SCS1
READ SCS1
SCRF = 1
SCRF = 1
BYTE 3
BYTE 3
OR = 1
OR = 0
BYTE 4
BYTE 4
Freescale Semiconductor
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