MC908GP16CBE Freescale Semiconductor, MC908GP16CBE Datasheet - Page 82

• Manufacturer Part Number: MC908GP16CBE
• Description: IC MCU 16K FLASH 42-SDIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP16CBE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 31
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.2 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Configuration Register (CONFIG)
OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit
SCIBDSRC — SCI Baud Rate Clock Source Bit
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
82
OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the
OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful
for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See
Clock Generator Module (CGM)
SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at
which the SCI operates.
COPRS selects the COP timeout period. Reset clears COPRS. (See
Properly
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP. (See
3.5.2 Stop
LVIRSTD disables the reset signal from the LVI module. (See
LVIPWRD disables the LVI module. (See
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
(COP).)
Note: LVI5OR3 bit is only reset via POR (power-on reset)
Mode.)
Address:
Reset:
Read:
Write:
COPRS
$001F
Bit 7
0
Figure 6-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
MC68HC908GP32 Data Sheet, Rev. 10
subsection
LVIRSTD
5
0
Chapter 11 Low-Voltage Inhibit
3.5.2 Stop
LVIPWRD
4
0
LVI5OR3
See Note
Mode.)
3
Chapter 11 Low-Voltage Inhibit
SSREC
2
0
Chapter 7 Computer Operating
(LVI).)
STOP
1
0
Freescale Semiconductor
COPD
Bit 0
0
(LVI).)
3.5