MC908GP16CBE Freescale Semiconductor, MC908GP16CBE Datasheet - Page 87
MC908GP16CBE
Manufacturer Part Number
MC908GP16CBE
Description
IC MCU 16K FLASH 42-SDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GP32CFBE.pdf
(266 pages)
Specifications of MC908GP16CBE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
31
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
42-DIP (0.600", 15.24mm)
Processor Series
HC08GP
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
8.2 MHz
Number Of Programmable I/os
33
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908GP16CBE
Manufacturer:
FREESCALE
Quantity:
20 000
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7.3.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. (See
Chapter 6 Configuration Register
7.3.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register.
(See
7.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to
$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
7.5 Interrupts
The COP does not generate CPU interrupt requests.
7.6 Monitor Mode
When monitor mode is entered with V
on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not
having V
7.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
7.7.1 Wait Mode
The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear
the COP counter in a CPU interrupt routine.
7.7.2 Stop Mode
Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP
immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering
or exiting stop mode.
Freescale Semiconductor
Chapter 6 Configuration Register
TST
on the IRQ pin, the COP is automatically disabled until a POR occurs.
Address: $FFFF
Reset:
Read:
Write:
Bit 7
Figure 7-2. COP Control Register (COPCTL)
(CONFIG).)
6
MC68HC908GP32 Data Sheet, Rev. 10
TST
(CONFIG).)
on the IRQ pin, the COP is disabled as long as V
5
Low byte of reset vector
Unaffected by reset
Clear COP counter
4
3
2
1
COP Control Register
Bit 0
TST
remains
87
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