MC908GZ32VFAER Freescale Semiconductor, MC908GZ32VFAER Datasheet - Page 166
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MC908GZ32VFAER
Manufacturer Part Number
MC908GZ32VFAER
Description
IC MCU 8BIT 32K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GZ60CFJE.pdf
(352 pages)
Specifications of MC908GZ32VFAER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GZ32VFAER
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MSCAN08 Controller (MSCAN08)
12.13.11 MSCAN08 Transmit Error Counter
This read-only register reflects the status of the MSCAN08 transmit error counter.
12.13.12 MSCAN08 Identifier Acceptance Registers
On reception each message is written into the background receive buffer. The CPU is only signalled to
read the message, however, if it passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming
messages in a bit by bit manner.
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only
the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are applied.
166
Address:
CIDAR0 Address: $0510
CIDAR1 Address: $050511
CIDAR2 Address: $0512
CIDAR3 Address: $0513
Both error counters may only be read when in sleep or soft reset mode.
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
TXERR7
$050F
Bit 7
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
Bit 7
AC7
0
Figure 12-26. Transmit Error Counter (CTXERR)
Figure 12-27. Identifier Acceptance Registers
= Unimplemented
TXERR6
AC6
AC6
AC6
AC6
6
0
6
6
6
6
TXERR5
AC5
AC5
AC5
AC5
(CIDAR0–CIDAR3)
5
0
5
5
5
5
NOTE
TXERR4
Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
AC4
AC4
AC4
AC4
4
0
4
4
4
4
TXERR3
AC3
AC3
AC3
AC3
3
0
3
3
3
3
TXERR2
AC2
AC2
AC2
AC2
2
0
2
2
2
2
TXERR1
AC1
AC1
AC1
AC1
1
0
1
1
1
1
Freescale Semiconductor
TXERR0
Bit 0
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
Bit 0
AC0
0
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