MC908GR16AVFAER Freescale Semiconductor, MC908GR16AVFAER Datasheet - Page 76

• Manufacturer Part Number: MC908GR16AVFAER
• Description: IC MCU 8BIT 16K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16AVFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Configuration Register (CONFIG)
TBMCLKSEL— Timebase Clock Select Bit
OSCENINSTOP — Oscillator Enable In Stop Mode Bit
ESCIBDSRC — SCI Baud Rate Clock Source Bit
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
76
TBMCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables
the extra prescaler and clearing this bit disables it. See
a more detailed description of the external clock operation.
OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module
the reset of the MCU stops. See
to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator
in stop mode.
ESCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See
Communications Interface (ESCI)
COPRS selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module. See
1 = Enables extra divide-by-128 prescaler in timebase module
0 = Disables extra divide-by-128 prescaler in timebase module
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal bus clock used as clock source for SCI (default)
0 = External oscillator used as clock source for SCI
1 = COP timeout period = 8176 COPCLK cycles
0 = COP timeout period = 262,128 COPCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
Note: LVI5OR3 bit is only reset via POR (power-on reset).
Address:
Reset:
Read:
Write:
COPRS
$001F
Bit 7
0
Figure 5-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
Chapter 17 Timebase Module
Module.
LVIRSTD
(CGM). This function is used to keep the timebase running while
5
0
LVIPWRD
4
0
LVI5OR3
See note
Chapter 4 Clock Generator Module (CGM)
3
Chapter 11 Low-Voltage Inhibit
(TBM). When clear, oscillator will cease
Chapter 14 Enhanced Serial
SSREC
2
0
Chapter 6 Computer Operating
STOP
1
0
Freescale Semiconductor
COPD
Bit 0
0
(LVI).
for