MC908GR16AVFAER Freescale Semiconductor, MC908GR16AVFAER Datasheet - Page 67

• Manufacturer Part Number: MC908GR16AVFAER
• Description: IC MCU 8BIT 16K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GR16AVFAER

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 37
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GR
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 4
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.5.1 PLL Control Register
The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base
clock selector bit, and the VCO power-of-two range selector bits.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Interrupt Flag Bit
PLLON — PLL On Bit
BCS — Base Clock Select Bit
Freescale Semiconductor
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting
the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE
cannot be written and reads as 0. Reset clears the PLLIE bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the
PLLIE bit also is set. PLLF always reads as 0 when the AUTO bit in the PLL bandwidth control register
(PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be
cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up.
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock,
CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one
source clock to the other. During the transition, CGMOUT is held in stasis. (See
Selector
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
1 = PLL on
0 = PLL off
1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT
Circuit.) Reset clears the BCS bit.
Address:
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base clock
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and
Reset:
Read:
Write:
$0036
PLLIE
Bit 7
0
= Unimplemented
Figure 4-4. PLL Control Register (PCTL)
PLLF
6
0
MC68HC908GR16A Data Sheet, Rev. 1.0
PLLON
5
1
NOTE
NOTE
BCS
4
0
R
R
3
0
= Reserved
R
2
0
VPR1
4.3.8 Base Clock Selector
1
0
4.3.8 Base Clock
VPR0
Bit 0
0
CGM Registers
67