S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 166

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Background Debug Module (S12SBDMV1)
When entering background debug mode, the BDM CCR holding register is used to save the condition code
register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode.
The BDM CCR holding register can be written to modify the CCR value.
5.3.2.2
Register Global Address 0x3_FF08
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
5.3.3
The family ID is an 8-bit value located in the firmware ROM (at global address: 0x3_FF0F). The read-only
value is a unique family ID which is 0xC2 for devices with an HCS12S core.
5.4
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see
166
BPP[3:0]
Reset
BPAE
Field
3–0
7
W
R
Functional Description
Section 5.4.4, “Standard BDM Firmware
Family ID Assignment
BPAE
BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and
firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD
and WRITE_BD) can not be used for global accesses even if the BGAE bit is set.
0 BDM Program Paging disabled
1 BDM Program Paging enabled
BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed
information regarding the program page window scheme, please refer to the S12S_MMC Block Guide.
BDM Program Page Index Register (BDMPPR)
7
0
Section 5.4.3, “BDM Hardware
= Unimplemented, Reserved
6
0
0
Figure 5-5. BDM Program Page Register (BDMPPR)
Section 5.4.3, “BDM Hardware
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 5-3. BDMPPR Field Descriptions
5
0
0
Commands”) and in secure mode (see
4
0
0
Commands”. The CPU resources referred to are the
Description
BPP3
Commands”. Target system memory
3
0
BPP2
2
0
Freescale Semiconductor
BPP1
1
0
Section 5.4.1,
BPP0
0
0