S9S12HY64J0MLL Freescale Semiconductor, S9S12HY64J0MLL Datasheet - Page 135

• Manufacturer Part Number: S9S12HY64J0MLL
• Description: MCU 64K FLASH AUTO 100-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12HY64J0MLL

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LCD, Motor control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-LQFP
• Controller Family/series: S12
• No. Of I/o's: 80
• Ram Memory Size: 4KB
• Cpu Speed: 64MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Processor Series: S12HY
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12HY64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 3 S12P Memory Map Control (S12PMMCV1)
3.1
The S12PMMC module controls the access to all internal memories and peripherals for the CPU12 and
S12SBDM module. It regulates access priorities and determines the address mapping of the on-chip
ressources.
3.1.1
Freescale Semiconductor
Local Addresses
Global Addresse
Aligned Bus Access
Misaligned Bus Access
NS
SS
Unimplemented Address Ranges Address ranges which are not mapped to any on-chip ressource.
P-Flash
D-Plash
NVM
IFR
(Item No.)
Rev. No.
01.03
01.04
01.04
Introduction
(Submitted By)
Figure 3-1
Glossary
18.APR.2008
27.Jun.2008
11.Jul.2008
Term
Date
shows a block diagram of the S12PMMC module.
Section 3.3.2.3,
“Program Page
Index Register
Section 3.5.1,
“Implemented
Memory
(PPAGE)”
Sections
Affected
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Map”
Address within the CPU12’s Local Address Map
Address within the Global Address Map
Bus access to an even address.
Bus access to an odd address.
Normal Single-Chip Mode
Special Single-Chip Mode
Program Flash
Data Flash
Non-volatile Memory; P-Flash or D-Flash
NVM Information Row. Refer to FTMRC Block Guide
Table 3-1. Revision History Table
Table 3-2. Glossary Of Terms
Corrected the address offset of the PPAGE register
Removed “Table 1-9. MC9S12P Derivatives”
Removed references to the MMCCTL1 register
Substantial Change(s)
Definition
(Figure
(on page
3-10)
(Figure
3-140)
3-10)
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