MC9S08AW32CFGE Freescale Semiconductor, MC9S08AW32CFGE Datasheet - Page 98

• Manufacturer Part Number: MC9S08AW32CFGE
• Description: IC MCU 32K FLASH 44-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AW32CFGE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: S08AW
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 8
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AW60E
• Minimum Operating Temperature: - 55 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44LQFP
• Family Name: HCS08
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

1
1
Chapter 6 Parallel Input/Output
6.7.8
In addition to the I/O control, port D pins are controlled by the registers listed below.
98
PTDPE[3:0]
PTDSE[3:0]
Bits 7 through 4 are reserved bits that must always be written to 0.
Bits 7 through 4 are reserved bits that must always be written to 0.
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
Port D Pin Control Registers (PTDPE, PTDSE, PTDDS)
Internal Pullup Enable for Port D Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTD pin. For port D pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port D bit n.
1 Internal pullup device enabled for port D bit n.
Output Slew Rate Control Enable for Port D Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTD pin. For port D pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port D bit n.
1 Output slew rate control enabled for port D bit n.
R
R
0
0
7
7
Figure 6-28. Output Slew Rate Control Enable for Port D (PTDSE)
Figure 6-27. Internal Pullup Enable for Port D (PTDPE)
R
R
0
0
6
6
Table 6-18. PTDPE Register Field Descriptions
Table 6-19. PTDSE Register Field Descriptions
MC9S08AC16 Series Data Sheet, Rev. 8
R
R
0
0
5
5
R
R
0
0
4
4
Description
Description
PTDPE3
PTDSE3
3
0
3
0
PTDPE2
PTDSE2
0
0
2
2
1
PTDPE1
PTDSE1
1
Freescale Semiconductor
0
0
1
1
PTDPE0
PTDSE0
0
0
0
0