MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 3
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MC9S08DZ128 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
On-Chip Memory
Power-Saving Modes
Clock Source Options
System Protection
Development Support
• 40-MHz HCS08 CPU (20-MHz bus)
• HC08 instruction set with added BGND instruction
• Support for up to 32 interrupt/reset sources
• FLASH read/program/erase over full operating voltage
• EEPROM in-circuit programmable memory; 8-byte
• Random-access memory (RAM)
• Two very low power stop modes
• Reduced power wait mode
• Very low power real time interrupt for use in run, wait,
• Oscillator (XOSC) — Loop-control Pierce oscillator;
• Multi-purpose Clock Generator (MCG) — PLL and
• Watchdog computer operating properly (COP) reset
• Low-voltage detection with reset or interrupt; selectable
• Illegal opcode detection with reset
• Illegal address detection with reset
• FLASH and EEPROM block protect
• Loss-of-lock protection
• Single-wire background debug interface
• On-chip, in-circuit emulation (ICE) with real-time bus
EEPROM
FLASH
and temperature
single-page or 4-byte dual-page erase sector; Program
and Erase while executing FLASH; Erase abort
RAM
and stop
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
FLL modes; reference clock with nonvolatile trim
(0.2% resolution, 1.5% tolerance over temperature with
internal temperature compensation); External reference
with oscillator/resonator options
with option to run from backup dedicated 1-kHz
internal clock source or bus clock; with optional
windowed operation
trip points
capture
MC9S08
DZ128
128K
2K
8K
MC9S08
DZ96
96K
2K
6K
MC9S08
DV128
128K
6K
—
MC9S08
DV96
96K
4K
—
Peripherals
Input/Output
Package Options
• ADC — 24-channel, 12-bit resolution, 2.5 μs
• ACMPx — Two analog comparators with selectable
• MSCAN — CAN protocol - Version 2.0 A, B; standard
• SCIx — Two SCIs supporting LIN 2.0 Protocol and
• SPIx — Up to two SPIs; Full-duplex or single-wire
• IICx — Up to two IICs; Up to 100 kbps with maximum
• TPMx — One 6-channel (TPM1), one 2-channel
• RTC — (Real-time counter) 8-bit modulus counter with
• Up to 87 general-purpose input/output (I/O) pins and
• Up to 32 interrupt pins with selectable polarity on each
• Hysteresis and configurable pull device on all input
• Configurable slew rate and drive strength on all output
• 100-pin low-profile quad flat-pack(LQFP) — 14x14
• 64-pin low-profile quad flat-pack (LQFP) — 10x10 mm
• 48-pin low-profile quad flat-pack (LQFP) — 7x7 mm
conversion time, automatic compare function,
temperature sensor, internal bandgap reference channel
interrupt on rising, falling, or either edge of comparator
output; compare option to fixed internal bandgap
reference voltage; runs in stop3 mode
and extended data frames; Support for remote frames;
Five receive buffers with FIFO storage scheme; Flexible
identifier acceptance filters programmable as: 2 x
32-bit, 4 x 16-bit, or 8 x 8-bit
SAE J2602 protocols; Full duplex non-return to zero
(NRZ); Master extended break generation; Slave
extended break detection; Wakeup on active edge
bidirectional; Double-buffered transmit and receive;
Master or Slave mode; MSB-first or LSB-first shifting
bus loading; Multi-master operation; Programmable
slave address; General Call Address; Interrupt driven
byte-by-byte data transfer
(TPM2) and one 4-channel (TPM3); Selectable input
capture, output compare, or buffered edge- and
center-aligned PWM on each channel.
binary or decimal based prescaler; Real-time clock
capabilities using external crystal and RTC for precise
time base, time-of-day, calendar or task scheduling
functions; Free running on-chip low power oscillator
(1 kHz) for cyclic wake-up without external
components
1 input-only pin
pin
pins.
pins.
mm
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