MC9S08DZ48AMLF Freescale Semiconductor, MC9S08DZ48AMLF Datasheet - Page 155
![MCU 8BIT 48K FLASH EE 48-LQFP](/photos/37/62/376254/lqfp-48_sml.jpg)
MC9S08DZ48AMLF
Manufacturer Part Number
MC9S08DZ48AMLF
Description
MCU 8BIT 48K FLASH EE 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ48AMLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Eeprom Size
1.5K x 8
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
3 KB
Interface Type
CAN, I2C, SCI, SPI
Number Of Programmable I/os
40
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ48AMLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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BPL rel
BRA rel
BRCLR n,opr8a,rel
BRN rel
BRSET n,opr8a,rel
BSET n,opr8a
BSR rel
CALL page, opr16a
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
CLC
CLI
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Freescale Semiconductor
Source
Form
Branch if Plus (if N = 0)
Branch Always (if I = 1)
Branch if Bit n in Memory Clear (if (Mn) = 0)
Branch Never (if I = 0)
Branch if Bit n in Memory Set (if (Mn) = 1)
Set Bit n in Memory (Mn ← 1)
Branch to Subroutine
Call Subroutine
Compare and...
Clear Carry Bit (C ← 0)
Clear Interrupt Mask Bit (I ← 0)
Clear
push (PCL); SP ← (SP) – $0001
push (PCH); SP ← (SP) – $0001
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
PC ← (PC) + rel
PC ← (PC) + $0002
Operation
Table 7-2. Instruction Set Summary (Sheet 3 of 9)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
MC9S08DZ128 Series Data Sheet, Rev. 1
REL
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
EXT
DIR
IMM
IMM
IX1+
IX+
SP1
INH
INH
DIR
INH
INH
INH
IX1
IX
SP1
9E 61
9E 6F
Object Code
2A rr
20 rr
01
03
05
07
09
0B
0D
0F
21 rr
00
02
04
06
08
0A
0C
0E
10
12
14
16
18
1A
1C
1E
AD rr
AC pg hhll
31
41
51
61
71
98
9A
3F
4F
5F
8C
6F
7F
dd
ff
ff
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd
dd
dd
dd
dd
dd
dd
dd
dd rr
ii rr
ii rr
ff rr
rr
ff rr
Chapter 7 Central Processor Unit (S08CPUV5)
3
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
8
1
1
5
1
1
1
5
4
6
3
5
4
4
5
5
6
ppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
ssppp
rfwpp
p
p
p
rfwpp
rfwp
prfwpp
ppp
ppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
ppsssppp
rpppp
pppp
pppp
rpppp
rfppp
prpppp
p
p
Cyc-by-Cyc
Details
V 1 1 H
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
– 1 1 –
0 1 1 –
on CCR
Affect
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – 0
0 – – –
– 0 1 –
I N Z C
– – – ↕
– – – ↕
155
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