S9S08DZ32F1MLH Freescale Semiconductor, S9S08DZ32F1MLH Datasheet - Page 106

• Manufacturer Part Number: S9S08DZ32F1MLH
• Description: MCU 32K FLASH MASK AUTO 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of S9S08DZ32F1MLH

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LQFP
• Processor Series: S08D
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
Chapter 6 Parallel Input/Output Control
6.5.5.3
6.5.5.4
Note: Slew rate reset default values may differ between engineering samples and final production parts. Always initialize slew
106
PTEPE[7:0]
PTESE[7:0]
Reset:
Reset:
PTESE1 has no effect on the input-only PTE1 pin.
Field
Field
7:0
7:0
rate control to the desired value to ensure correct operation.
W
W
R
R
PTEPE7
PTESE7
Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up device enabled for port E bit n.
Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
Port E Pull Enable Register (PTEPE)
0
Port E Slew Rate Enable Register (PTESE)
0
7
7
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are configured.
PTEPE6
PTESE6
Figure 6-34. Internal Pull Enable for Port E Register (PTEPE)
Figure 6-35. Slew Rate Enable for Port E Register (PTESE)
0
0
6
6
Table 6-32. PTEPE Register Field Descriptions
Table 6-33. PTESE Register Field Descriptions
PTEPE5
PTESE5
MC9S08DZ60 Series Data Sheet, Rev. 4
0
0
5
5
PTEPE4
PTESE4
NOTE
0
0
4
4
Description
Description
PTEPE3
PTESE3
3
0
3
0
PTEPE2
PTESE2
0
0
2
2
PTESE1
PTEPE1
Freescale Semiconductor
0
0
1
1
1
PTEPE0
PTESE0
0
0
0
0