C8051F226-GQR Silicon Laboratories Inc, C8051F226-GQR Datasheet - Page 44
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C8051F226-GQR
Manufacturer Part Number
C8051F226-GQR
Description
IC 8051 MCU 8K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F2xxr
Specifications of C8051F226-GQR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 32x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
C8051F2x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
3 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F226DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 32 Channel
For Use With
336-1241 - DEV KIT F220/221/226/230/231/236
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F226-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F2xx
44
Bit7:
Bit6:
Bit5:
Bit4:
Bits3–2: ADSTM1–0: ADC Start of Conversion Mode Bits
Bit1:
Bit0:
ADCEN
R/W
Bit7
ADCEN: ADC Enable Bit
0: ADC Disabled. ADC is in low power shutdown.
1: ADC Enabled. ADC is active and ready for data conversions.
ADCTM: ADC Track Mode Bit
0: When the ADC is enabled, tracking is continuous unless a conversion is in process
1: Tracking Defined by ADSTM1–0 bits
ADCINT: ADC Conversion Complete Interrupt Flag (cleared by software).
0: ADC has not completed a data conversion since the last time this flag was cleared
1: ADC has completed a data conversion
ADBUSY: ADC Busy Bit
Read
0: ADC Conversion complete or no valid data has been converted since a reset. The falling
edge of ADBUSY generates an interrupt when enabled.
1: ADC Busy converting data
Write
0: No effect
1: Starts ADC Conversion if ADSTM1–0 = 00b
00: ADC conversion started upon a write of 1 to ADBUSY
01: RESERVED
10: RESERVED
11: ADC conversions initiated on overflows of Timer 2
ADWINT: ADC Window Compare Interrupt Flag
0: ADC Window Comparison Data match has not occurred
1: ADC Window Comparison Data match occurred
ADLJST: ADC Left Justify Data Bit
0: Data in ADC0H:ADC0L registers are right justified.
1: Data in ADC0H:ADC0L registers are left justified.
SFR Definition 6.3. ADC0CN: ADC Control (‘F220/1/6 and ‘F206)
ADCTM
R/W
Bit6
ADSTM1–0:
00: Tracking starts with the write of 1 to ADBUSY and lasts for 3 SAR clocks
01: RESERVED
10: RESERVED
11: Tracking started by the overflow of Timer 2 and last for 3 SAR clocks
ADCINT ADBUSY ADSTM1 ADSTM0 ADWINT
R/W
Bit5
R/W
Bit4
R/W
Bit3
Rev. 1.6
R/W
Bit2
R/W
Bit1
(bit addressable)
ADLJST
R/W
Bit0
SFR Address:
Reset Value
00000000
0xE8