C8051F226-GQR Silicon Laboratories Inc, C8051F226-GQR Datasheet - Page 117

• Manufacturer Part Number: C8051F226-GQR
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F226-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 32x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F226DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 32 Channel
• For Use With: 336-1241 - DEV KIT F220/221/226/230/231/236
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16. UART
Description
The CIP-51 includes a serial port (UART) capable of asynchronous transmission. The UART can function
in full duplex mode. In all modes, receive data is buffered in a holding register. This allows the UART to
start reception of a second incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the
SFRs. The single SBUF location provides access to both transmit and receive registers. Reads access
the Receive register and writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a
Transmit Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Inter-
rupt flag, RI (SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manu-
ally by software. This allows software to determine the cause of the UART interrupt (transmit complete or
receive complete).
S
M
O
D
Overflow
Overflow
Timer 1
Timer 2
PCON
SYSCLK
2
M
S
0
Baud Rate Generation Logic
SMOD
1
0
S
M
1
M
S
2
SCON
R
E
N
32
64
12
T
B
8
R
B
8
T
I
SMOD
TCLK
RCLK
R
I
0
1
0
1
1
0
16
16
R
C
K
L
T2CON
Figure 16.1. UART Block Diagram
T
C
L
K
SFR Bus
00
01
10
11
00
01
10
11
SM0, SM1
{MODE}
Write to
SBUF
Rev. 1.6
Tx Clock
Rx Clock
Start
Start
Bit Detector
Interrupt
Serial
Port
D
TB8
SET
CLR
Stop Bit
Q
Gen.
SBUF
Read
TI
RI
Tx Control
Tx IRQ
Rx IRQ
Rx Control
Zero Detector
SFR Bus
Input Shift Register
SBUF
SBUF
Enable
REN
Shift
(9 bits)
0x1FF
MSB
RB8
Load SBUF
SBUF
Data
Send
Load
Shift
Shift
RX
TX
C8051F2xx
Port0 MUX
Port0 MUX
P0.0
P0.1
Port I/O
117