C8051F226-GQR Silicon Laboratories Inc, C8051F226-GQR Datasheet - Page 126

IC 8051 MCU 8K FLASH 48TQFP

C8051F226-GQR

Manufacturer Part Number
C8051F226-GQR
Description
IC 8051 MCU 8K FLASH 48TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F2xxr
Datasheets

Specifications of C8051F226-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
32
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 32x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
C8051F2x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
32
Number Of Timers
3 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F226DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 32 Channel
For Use With
336-1241 - DEV KIT F220/221/226/230/231/236
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F226-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F2xx
Setting TR0 does not reset the timer register. The timer register should be initialized to the desired value
before enabling the timer.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0.
17.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The coun-
ter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
126
X = Don’t Care
TR0
SYSCLK
0
1
1
1
/INT0
T0
GATE0
GATE0
TR0
PORT0
X
0
1
1
MUX
PORT0
MUX
12
0
1
/INT0
Figure 17.1. T0 Mode 0 Block Diagram
X
X
0
1
CKCON
M
T
2
1
0
M
T
1
Disabled
Enabled
Disabled
Enabled
M
T
0
Counter/Timer
G
A
T
E
1
Rev. 1.6
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
(8 bits)
TH0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Interrupt

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