C8051F220-GQ Silicon Laboratories Inc, C8051F220-GQ Datasheet - Page 74

• Manufacturer Part Number: C8051F220-GQ
• Description: IC 8051 MCU 8K FLASH 48TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F220-GQ

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 48-TQFP, 48-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 32
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 32x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F206DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 8-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1241 - DEV KIT F220/221/226/230/231/236
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1238

C8051F2xx
9.4.
Interrupt Handler
The CIP-51 includes an extended interrupt system supporting up to 22 interrupt sources with two priority
levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies
according to the specific version of the device. Each interrupt source has one or more associated inter-
rupt-pending flag(s) located in an SFR. When a peripheral or external source meets a valid interrupt con-
dition, the associated interrupt-pending flag is set to logic 1.
If interrupts are enabled for the source, an interrupt request is generated when the interrupt-pending flag is
set. As soon as execution of the current instruction is complete, the CPU generates an LCALL to a prede-
termined address to begin execution of an interrupt service routine (ISR). Each ISR must end with an
RETI instruction, which returns program execution to the next instruction that would have been executed if
the interrupt request had not occurred. If interrupts are not enabled, the interrupt-pending flag is ignored by
the hardware and program execution continues as normal. (The interrupt-pending flag is set to logic 1
regardless of the interrupt's enable/disable state.)
Each interrupt source can be individually enabled or disabled through the use of an associated interrupt
enable bit in an SFR (IE–EIE2). However, interrupts must first be globally enabled by setting the EA bit
(IE.7) to logic 1 before the individual interrupt enables are recognized. Setting the EA bit to logic 0 dis-
ables all interrupt sources regardless of the individual interrupt-enable settings.
Some interrupt-pending flags are automatically cleared by the hardware when the CPU vectors to the ISR.
However, most are not cleared by the hardware and must be cleared by software before returning from the
ISR. If an interrupt-pending flag remains set after the CPU completes the return-from-interrupt (RETI)
instruction, a new interrupt request will be generated immediately and the CPU will re-enter the ISR after
the completion of the next instruction.
9.4.1. MCU Interrupt Sources and Vectors
The MCU allocates 9 interrupt sources to on-chip peripherals. Software can simulate an interrupt by set-
ting any interrupt-pending flag to logic 1. If interrupts are enabled for the flag, an interrupt request will be
generated and the CPU will vector to the ISR address associated with the interrupt-pending flag. The
MCU interrupt sources, associated vector addresses, priority order and control bits are summarized in
Table 9.4. Refer to the datasheet section associated with a particular on-chip peripheral for information
regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
9.4.2. External Interrupts
The two external interrupt sources (/INT0 and /INT1) are configurable as active-low level-sensitive or
active-low edge-sensitive inputs depending on the setting of IT0 (TCON.0) and IT1 (TCON.2).
IE0
(TCON.1) and IE1 (TCON.3) serve as the interrupt-pending flag for the /INT0 and /INT1 external interrupts,
respectively. If an /INT0 or /INT1 external interrupt is configured as edge-sensitive, the corresponding
interrupt-pending flag is automatically cleared by the hardware when the CPU vectors to the ISR. When
configured as level sensitive, the interrupt-pending flag follows the state of the external interrupt's input pin.
The external interrupt source must hold the input active until the interrupt request is recognized. It must
then deactivate the interrupt request before execution of the ISR completes or another interrupt request
will be generated.
9.4.3. Software Controlled Interrupts
The C8051F2xx family of devices features four Software Controlled Interrupts controlled by flags located in
the Software Controlled Interrupt Flag Register (SWCINT). See SFR Definition 9.7. When a logic '1' is
written to a Software-Controlled Interrupt Flag, the CIP-51 will jump to an associated interrupt service vec-
tor (see Table 9.4, “Interrupt Summary,” on page 75). These interrupt flags must be cleared by software.
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