MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 329
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Chapter 10
Pulse-Width Modulator (PWM8B6CV1) Block Description
10.1
The pulse width modulation (PWM) definition is based on the HC12 PWM definitions. The PWM8B6CV1
module contains the basic features from the HC11 with some of the enhancements incorporated on the
HC12, that is center aligned output mode and four available clock sources. The PWM8B6CV1 module has
six channels with independent control of left and center aligned outputs on each channel.
Each of the six PWM channels has a programmable period and duty cycle as well as a dedicated counter.
A flexible clock select scheme allows a total of four different clock sources to be used with the counters.
Each of the modulators can create independent continuous waveforms with software-selectable duty rates
from 0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs
10.1.1
10.1.2
There is a software programmable option for low power consumption in wait mode that disables the input
clock to the prescaler.
In freeze mode there is a software programmable option to disable the input clock to the prescaler. This is
useful for emulation.
Freescale Semiconductor
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Six independent PWM channels with programmable period and duty cycle
Dedicated counter for each PWM channel
Programmable PWM enable/disable for each channel
Software selection of PWM duty pulse polarity for each channel
Period and duty cycle are double buffered. Change takes effect when the end of the effective period
is reached (PWM counter reaches 0) or when the channel is disabled.
Programmable center or left aligned outputs on individual channels
Six 8-bit channel or three 16-bit channel PWM resolution
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies.
Programmable clock select logic
Emergency shutdown
Introduction
Features
Modes of Operation
S12P-Family Reference Manual, Rev. 1.13
329
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