MC9S12P96CFT Freescale Semiconductor, MC9S12P96CFT Datasheet - Page 188
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MC9S12P96CFT
Manufacturer Part Number
MC9S12P96CFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96CFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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S12S Debug Module (S12SDBGV2)
If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session
has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only on completion
of the subsequent trace (see
immediately.
If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing
trigger alignment.
6.4.7.2
If a TRIG triggers occur, the Final State is entered whereby tracing trigger alignment is defined by the
TALIGN bit. If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the
tracing session has completed, thus if Begin aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace (see
requested immediately. TRIG breakpoints are possible with a single write to DBGC1, setting ARM and
TRIG simultaneously.
6.4.7.3
If a TRIG trigger occurs after Begin aligned tracing has already started, then the TRIG no longer has an
effect. When the associated tracing session is complete, the breakpoint occurs. Similarly if a TRIG is
followed by a subsequent comparator channel match, it has no effect, since tracing has already started.
If a forced SWI breakpoint coincides with a BGND in user code with BDM enabled, then the BDM is
activated by the BGND and the breakpoint to SWI is suppressed.
6.4.7.3.1
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU
is executing out of BDM firmware, thus comparator matches and associated breakpoints are disabled. In
addition, while executing a BDM TRACE command, tagging into BDM is disabled. If BDM is not active,
the breakpoint gives priority to BDM requests over SWI requests if the breakpoint happens to coincide
with a SWI instruction in user code. On returning from BDM, the SWI from user code gets executed.
188
BRK
0
0
0
0
1
1
Breakpoints Generated Via The TRIG Bit
Breakpoint Priorities
DBG Breakpoint Priorities And BDM Interfacing
TALIGN
0
0
1
1
x
x
Table 6-42. Breakpoint Setup For CPU Breakpoints
Table
DBGBRK
S12P-Family Reference Manual, Rev. 1.13
6-42). If no tracing session is selected, breakpoints are requested
0
1
0
1
1
0
Table
Terminate tracing and generate breakpoint immediately on trigger
Fill Trace Buffer until trigger, then breakpoint request occurs
6-42). If no tracing session is selected, breakpoints are
Fill Trace Buffer until trigger then disarm (no breakpoints)
A breakpoint request occurs when Trace Buffer is full
Start Trace Buffer at trigger (no breakpoints)
Terminate tracing immediately on trigger
Start Trace Buffer at trigger
Breakpoint Alignment
Freescale Semiconductor
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