C8051F221-GQR Silicon Laboratories Inc, C8051F221-GQR Datasheet - Page 114

• Manufacturer Part Number: C8051F221-GQR
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F2xxr

Specifications of C8051F221-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 22
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 22x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F2x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F226DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 32 Channel
• For Use With: 336-1241 - DEV KIT F220/221/226/230/231/236
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F2xx
114
Bit7:
Bit6:
Bits5–3: BC2–BC0: SPI Bit Count.
Bits2–0:
CKPHA
R/W
Bit7
CKPHA: SPI Clock Phase.
This bit controls the SPI clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
CKPOL: SPI Clock Polarity.
This bit controls the SPI clock polarity. 
0: SCK line low in idle state.
1: SCK line high in idle state.
Indicates which of the up to 8 bits of the SPI word have been transmitted.
These three bits determine the number of bits to shift in/out of the SPI shift register during a
data transfer in master mode. They are ignored in slave mode.
SPIFRS2–SPIFRS0: SPI Frame Size. 
0
0
0
0
1
1
1
1
CKPOL
0
0
0
0
1
1
1
1
R/W
Bit6
BC2 – BC0
SPIFRS
SFR Definition 15.1. SPI0CFG: SPI Configuration
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BC2
Bit5
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BC1
Bit4
R
Bit Transmitted
Bits Shifted
Bit 7 (MSB)
Bit 0 (LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
1
2
3
4
5
6
7
8
Rev. 1.6
BC0
Bit3
R
SPIFRS2 SPIFRS1 SPIFRS0
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
Reset Value
00000111
0x9A