MCR908JL3ECFAE Freescale Semiconductor, MCR908JL3ECFAE Datasheet - Page 130
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MCR908JL3ECFAE
Manufacturer Part Number
MCR908JL3ECFAE
Description
IC MCU 4K FLASH 8MHZ 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JK1ECDWE.pdf
(180 pages)
Specifications of MCR908JL3ECFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCR908JL3ECFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Break Module (BREAK)
15.3.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module status bits can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. (See
subsection for each module.)
15.3.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in progress. If the break address
register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
15.3.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
15.3.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V
130
Note: Writing a 0 clears SBSW.
Addr.
$FE0C
$FE0D
$FE0E
$FE00
$FE03
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD
($FEFC:$FEFD in monitor mode)
Break Status and Control
Register Name
Break Status Register
Break Address High
Break Flag Control
Break Address low
(BRKSCR)
Register
Register
Register
Register
(BRKH)
(BFCR)
(BRKL)
(BSR)
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Figure 15-2. Break I/O Register Summary
5.7.3 Break Flag Control Register (BFCR)
MC68HC908JL3E Family Data Sheet, Rev. 4
BRKE
BCFE
Bit15
Bit 7
Bit7
R
0
0
0
0
= Unimplemented
BRKA
Bit14
Bit6
R
R
6
0
0
0
TST
Bit13
Bit5
R
R
5
0
0
0
0
is present on the RST pin.
Bit12
Bit4
R
R
R
4
0
0
0
0
= Reserved
Bit11
Bit3
R
R
3
0
0
0
0
and see the Break Interrupts
Bit10
Bit2
R
R
2
0
0
0
0
Freescale Semiconductor
See note
SBSW
Bit9
Bit1
R
1
0
0
0
0
0
Bit 0
Bit8
Bit0
R
R
0
0
0
0
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