MC9S08AC48CFDE Freescale Semiconductor, MC9S08AC48CFDE Datasheet - Page 306

• Manufacturer Part Number: MC9S08AC48CFDE
• Description: IC MCU 8BIT 48K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08AC48CFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: S08AC
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SCI, SPI
• Operating Supply Voltage: - 0.3 V to + 5.8 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08AC60E, DEMOACEX, DEMOACKIT, DCF51AC256, DC9S08AC128, DC9S08AC16, DC9S08AC60, DEMO51AC256KIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Appendix A Electrical Characteristics and Timing Specifications
The average chip-junction temperature (T
where:
For most applications, P
(if P
Solving equations 1 and 2 for K gives:
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P
solving equations 1 and 2 iteratively for any value of T
A.5
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits and JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device
qualification ESD stresses were performed for the Human Body Model (HBM), the Machine Model (MM)
and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
306
D
(at equilibrium) for a known T
I/O
is neglected) is:
Human Body
ESD Protection and Latch-Up Immunity
T
θ
P
P
P
Model
JA
A
D
int
I/O
= Ambient temperature, °C
= P
= Package thermal resistance, junction-to-ambient, °C/W
= I
= Power dissipation on input and output pins — user determined
int
DD
+ P
× V
Series Resistance
Storage Capacitance
Number of Pulse per pin
I/O
I/O
DD
<< P
, Watts — chip internal power
Table A-4. ESD and Latch-up Test Conditions
K = P
int
A
and can be neglected. An approximate relationship between P
MC9S08AC60 Series Data Sheet, Rev. 2
. Using this value of K, the values of P
D
P
T
× (T
Description
D
J
= K ÷ (T
J
= T
A
) in °C can be obtained from:
+ 273°C) + θ
A
+ (P
J
D
+ 273°C)
× θ
A
JA
JA
.
)
× (P
D
)
2
Symbol
R1
C
–
D
and T
J
Value
1500
100
can be obtained by
3
Freescale Semiconductor
Unit
pF
Ω
D
Eqn. A-1
Eqn. A-2
Eqn. A-3
and T
J