C8051T612-GQ Silicon Laboratories Inc, C8051T612-GQ Datasheet - Page 124
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C8051T612-GQ
Manufacturer Part Number
C8051T612-GQ
Description
IC 8051 MCU 8K BYTE-PROG 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Specifications of C8051T612-GQ
Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
29
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051FT610DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1439
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T612-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051T612-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051T610/1/2/3/4/5/6/7
21.5. Special Function Registers for Accessing and Configuring Port I/O
All Port I/O are accessed through corresponding special function registers (SFRs) that are both byte
addressable and bit addressable. When writing to a Port, the value written to the SFR is latched to main-
tain the output data value at each pin. When reading, the logic levels of the Port's input pins are returned
regardless of the XBRn settings (i.e., even when the pin is assigned to another signal by the Crossbar, the
Port register can always read its corresponding Port I/O pin). The exception to this is the execution of the
read-modify-write instructions that target a Port Latch register as the destination. The read-modify-write
instructions when operating on a Port SFR are the following: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ
and MOV, CLR or SETB, when the destination is an individual bit in a Port SFR. For these instructions, the
value of the latch register (not the pin) is read, modified, and written back to the SFR.
Each Port has a corresponding PnSKIP register which allows its individual Port pins to be assigned to dig-
ital functions or skipped by the Crossbar. All Port pins used for analog functions, GPIO, or dedicated digital
functions such as the EMIF should have their PnSKIP bit set to 1.
The Port input mode of the I/O pins is defined using the Port Input Mode registers (PnMDIN). Each Port
cell can be configured for analog or digital I/O. This selection is required even for the digital resources
selected in the XBRn registers, and is not automatic.
The output driver characteristics of the I/O pins are defined using the Port Output Mode registers (PnMD-
OUT). Each Port Output driver can be configured as either open drain or push-pull. This selection is
required even for the digital resources selected in the XBRn registers, and is not automatic. The only
exception to this is the SMBus (SDA, SCL) pins, which are configured as open-drain regardless of the
PnMDOUT settings.
SFR Definition 21.3. P0: Port 0
SFR Address = 0x80; Bit-Addressable
124
Name
Reset
7:0
Bit
Type
Bit
P0[7:0]
Name
7
1
Port 0 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
6
1
Description
5
1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Rev 1.0
4
1
P0[7:0]
R/W
Write
3
1
2
1
0: P0.n Port pin is logic
LOW.
1: P0.n Port pin is logic
HIGH.
1
1
Read
0
1