MC9S08JM16CLC Freescale Semiconductor, MC9S08JM16CLC Datasheet - Page 176

• Manufacturer Part Number: MC9S08JM16CLC
• Description: MCU 8BIT 16K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Package: 32LQFP
• Family Name: HCS08
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
Inter-Integrated Circuit (S08IICV2)
176
If general call is enabled, a check must be done to determine whether the received address was a general call address (0x00).
If the received address was a general call address, then the general call must be handled by user software.
When 10-bit addressing is used to address a slave, the slave sees an interrupt following the first byte of the extended address.
User software must ensure that for this interrupt, the contents of IICD are ignored and not treated as a valid data transfer
Dummy Read
Switch to
from IICD
Rx Mode
Y
Transmitted
(Master Rx)
Byte to IICD
Addr Cycle
Write Next
Last Byte
RXAK=0
End of
?
?
?
Y
N
N
Stop Signal
TX
Generate
(MST = 0)
Y
N
Tx/Rx
Set TXACK =1
?
Figure 11-12. Typical IIC Interrupt Routine
Y
Byte to Be Read
Byte to Be Read
MC9S08JM16 Series Data Sheet, Rev. 2
Read Data
from IICD
and Store
2nd Last
RX
Last
?
?
N
N
Stop Signal
Generate
(MST = 0)
Y
Y
RTI
Master
Mode
Clear
IICIF
?
Write Data
(Read)
Set TX
to IICD
Mode
N
N
Y
Dummy Read
Clear ARBL
from IICD
IAAS=1
Set RX
SRW=1
Mode
Y
?
?
N
Address Transfer
(Write)
See Note 1
Tx Next
Byte
Y
Y
Y
Dummy Read
Arbitration
ACK from
from IICD
Receiver
Switch to
Freescale Semiconductor
IAAS=1
Rx Mode
TX/RX
Lost
?
?
?
?
N
N
N
Data Transfer
TX
See Note 2
Read Data
from IICD
and Store
RX