MC9S08JM16CLC Freescale Semiconductor, MC9S08JM16CLC Datasheet - Page 11

• Manufacturer Part Number: MC9S08JM16CLC
• Description: MCU 8BIT 16K FLASH 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM16CLC

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Controller Family/series: HCS08
• No. Of I/o's: 21
• Ram Memory Size: 1KB
• Cpu Speed: 48MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Package: 32LQFP
• Family Name: HCS08
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2
6.3
6.4
6.5
7.1
7.2
7.3
7.4
Freescale Semiconductor
Port Data and Data Direction ..........................................................................................................78
Pin Control ......................................................................................................................................79
Pin Behavior in Stop Modes ............................................................................................................79
Parallel I/O and Pin Control Registers ............................................................................................80
Introduction .....................................................................................................................................99
Programmer’s Model and CPU Registers .....................................................................................100
Addressing Modes .........................................................................................................................103
Special Operations .........................................................................................................................105
6.3.1 Internal Pullup Enable ......................................................................................................79
6.3.2 Output Slew Rate Control Enable .....................................................................................79
6.3.3 Output Drive Strength Select ............................................................................................79
6.5.1 Port A I/O Registers (PTAD and PTADD) ........................................................................80
6.5.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS) .................................................81
6.5.3 Port B I/O Registers (PTBD and PTBDD) ........................................................................82
6.5.4 Port B Pin Control Registers (PTBPE, PTBSE, PTBDS) .................................................83
6.5.5 Port C I/O Registers (PTCD and PTCDD) ........................................................................84
6.5.6 Port C Pin Control Registers (PTCPE, PTCSE, PTCDS) .................................................85
6.5.7 Port D I/O Registers (PTDD and PTDDD) .......................................................................87
6.5.8 Port D Pin Control Registers (PTDPE, PTDSE, PTDDS) ................................................88
6.5.9 Port E I/O Registers (PTED and PTEDD) ........................................................................89
6.5.10 Port E Pin Control Registers (PTEPE, PTESE, PTEDS) ..................................................91
6.5.11 Port F I/O Registers (PTFD and PTFDD) .........................................................................92
6.5.12 Port F Pin Control Registers (PTFPE, PTFSE, PTFDS) ...................................................93
6.5.13 Port G I/O Registers (PTGD and PTGDD) .......................................................................95
6.5.14 Port G Pin Control Registers (PTGPE, PTGSE, PTGDS) ................................................96
7.1.1 Features .............................................................................................................................99
7.2.1 Accumulator (A) .............................................................................................................100
7.2.2 Index Register (H:X) ......................................................................................................100
7.2.3 Stack Pointer (SP) ...........................................................................................................101
7.2.4 Program Counter (PC) ....................................................................................................101
7.2.5 Condition Code Register (CCR) .....................................................................................101
7.3.1 Inherent Addressing Mode (INH) ...................................................................................103
7.3.2 Relative Addressing Mode (REL) ..................................................................................103
7.3.3 Immediate Addressing Mode (IMM) ..............................................................................103
7.3.4 Direct Addressing Mode (DIR) ......................................................................................103
7.3.5 Extended Addressing Mode (EXT) ................................................................................104
7.3.6 Indexed Addressing Mode ..............................................................................................104
7.4.1 Reset Sequence ...............................................................................................................105
7.4.2 Interrupt Sequence ..........................................................................................................105
7.4.3 Wait Mode Operation ......................................................................................................106
7.4.4 Stop Mode Operation ......................................................................................................106
7.4.5 BGND Instruction ...........................................................................................................107
Central Processor Unit (S08CPUV2)
MC9S08JM16 Series Data Sheet, Rev. 2
Chapter 7
11