MC9S08QG8MPBE Freescale Semiconductor, MC9S08QG8MPBE Datasheet - Page 249
![IC MCU 8K FLASH 16-PDIP](/photos/12/33/123397/mc9s08qg8mpbe_sml.jpg)
MC9S08QG8MPBE
Manufacturer Part Number
MC9S08QG8MPBE
Description
IC MCU 8K FLASH 16-PDIP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08QG8CDTER.pdf
(314 pages)
Specifications of MC9S08QG8MPBE
Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-DIP (0.300", 7.62mm)
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI/SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Figure 17-3
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host should sample the bit level about 10 cycles after it started the bit time.
Freescale Semiconductor
SYNCHRONIZATION
PERCEIVED START
PERCEIVED START
(TARGET MCU)
SPEEDUP PULSE
(TARGET MCU)
TO BKGD PIN
BDC CLOCK
HOST DRIVE
TARGET MCU
UNCERTAINTY
TRANSMIT 1
TRANSMIT 0
BDC CLOCK
OF BIT TIME
OF BIT TIME
BKGD PIN
HOST
HOST
shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
Figure 17-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 17-2. BDC Host-to-Target Serial Bit Timing
HIGH-IMPEDANCE
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
R-C RISE
10 CYCLES
HOST SAMPLES BKGD PIN
TARGET SENSES BIT LEVEL
10 CYCLES
10 CYCLES
HIGH-IMPEDANCE
HIGH-IMPEDANCE
EARLIEST START
EARLIEST START
OF NEXT BIT
OF NEXT BIT
Development Support
247
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