C8051F305-GMR Silicon Laboratories Inc, C8051F305-GMR Datasheet - Page 175
C8051F305-GMR
Manufacturer Part Number
C8051F305-GMR
Description
IC 8051 MCU 2K FLASH 11QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Specifications of C8051F305-GMR
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
8
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
11-VQFN
For Use With
336-1444 - ADAPTER PROGRAM TOOLSTICK F300
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F305-GMR
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
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17.2. C2 Pin Sharing
The C2 protocol allows the C2 pins to be shared with user functions so that in-system debugging and
Flash programming functions may be performed. This is possible because C2 communication is typically
performed when the device is in the halt state, where all on-chip peripherals and user software are stalled.
In this halted state, the C2 interface can safely ‘borrow’ the C2CK (normally RST) and C2D (normally P0.7)
pins. In most applications, external resistors are required to isolate C2 interface traffic from the user appli-
cation. A typical isolation configuration is shown in Figure 17.1.
The configuration in Figure 17.1 assumes the following:
Additional resistors may be necessary depending on the specific application.
1. The user input (b) cannot change state while the target device is halted.
2. The RST pin on the target device is used as an input only.
/Reset (a)
Output (c)
Input (b)
Figure 17.1. Typical C2 Pin Sharing
C2 Interface Master
Rev. 2.9
C8051F300/1/2/3/4/5
C8051F300
C2CK (/RST)
C2D (P0.7)
175
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