C8051F305-GMR Silicon Laboratories Inc, C8051F305-GMR Datasheet - Page 162

• Manufacturer Part Number: C8051F305-GMR
• Description: IC 8051 MCU 2K FLASH 11QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F30xr

Specifications of C8051F305-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 11-VQFN
• For Use With: 336-1444 - ADAPTER PROGRAM TOOLSTICK F300
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

C8051F300/1/2/3/4/5
16.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate a pulse width modulated (PWM) output on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be set to ‘1’. When the count value in PCA0L overflows, the CEXn output will
be set to ‘0’ (see Figure 16.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to
0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s capture/compare high
byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn
register enables 8-bit Pulse Width Modulator mode. The duty cycle for 8-bit PWM Mode is given by
Equation 16.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
Using Equation 16.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
162
PCA0CPLn
Write to
Reset
PCA0CPHn
Write to
0
ENB
ENB
1
W
P
M
1
6
n
0
Figure 16.8. PCA 8-Bit PWM Mode Diagram
O
M
E
C
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
C
A
P
N
n
Equation 16.2. 8-Bit PWM Duty Cycle
M
A
T
n
O
G
T
n
W
DutyCycle
M
P
n
E
C
C
F
n
x
PCA Timebase
Enable
=
PCA0CPHn
Comparator
PCA0CPLn
Rev. 2.9
PCA0L

-------------------------------------------------- -
8-bit
256 PCA0CPHn
–
Overflow
256
match
S
R
SET
CLR

Q
Q
CEXn
Crossbar
Port I/O