MC9S08GT8ACFDE Freescale Semiconductor, MC9S08GT8ACFDE Datasheet - Page 277

• Manufacturer Part Number: MC9S08GT8ACFDE
• Description: IC MCU 8K FLASH 1K RAM 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFDE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 39
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

A.10.1
1
2
3
4
Freescale Semiconductor
Bus frequency (t
Real-time interrupt internal oscillator period
External reset pulse width
Reset low drive
Active background debug mode latch setup time
Active background debug mode latch hold time
IRQ pulse width
Port rise and fall time (load = 50 pF)
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of f
on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% V
Slew rate control disabled
Slew rate control enabled
Period (µs)
Control Timing
2
3
cyc
= 1/f
Bus
Parameter
1600
1400
1200
1000
1
800
600
400
200
)
0
–40
Figure A-11. Typical RTI Clock Period vs. Temperature
4
–20
DD
MC9S08GT16A/GT8A Data Sheet, Rev. 1
and 80% V
0
Table A-12. Control Timing
V
V
DD
DD
20
≥ 2.1 V
< 2.1 V
DD
levels. Temperature range –40°C to 125°C.
40
Temperature (°C)
t
60
Symbol
Rise
t
t
t
MSSU
t
rstdrv
t
f
extrst
t
MSH
ILIH
Bus
RTI
, t
Fall
80
100
f
f
1.5 x t
Self_reset
Self_reset
1.5 x
34 x
Min
750
25
25
—
—
0
0
cyc
120
Self_reset
140
Typical
1150
30
—
3
and then samples the level
= +3 Sigma
= Mean
= –3 Sigma
Electrical Characteristics
1550
Max
20
—
—
—
—
—
8
MHz
Unit
µs
ns
ns
ns
ns
ns
ns
277