C8051T605-GS Silicon Laboratories Inc, C8051T605-GS Datasheet - Page 92
![IC 8051 MCU 2K-EEPROM 14-SOIC](/photos/12/33/123368/c8051t605-gs_sml.jpg)
C8051T605-GS
Manufacturer Part Number
C8051T605-GS
Description
IC 8051 MCU 2K-EEPROM 14-SOIC
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T605-GS
Program Memory Type
OTP
Program Memory Size
2KB (2K x 8)
Package / Case
14-SOIC (3.9mm Width), 14-SOL
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SMBus/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1661-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T605-GS
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
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C8051T600/1/2/3/4/5/6
19. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost, even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For V
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. The Watchdog Timer is enabled with the system clock divided by 12 as its clock source. Pro-
gram execution begins at location 0x0000.
92
EXTCLK
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled
Frequency
Oscillator
Oscillator
Oscillator
External
Internal
Drive
Low
Px.x
Px.x
Clock Select
System
Clock
DD
Comparator 0
Monitor and power-on resets, the RST pin is driven low until the device
+
-
Figure 19.1. Reset Sources
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Core
Handler
WDT
PCA
EN
Rev. 1.2
VDD
System Reset
Supply
Monitor
+
-
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
Operation
EPROM
Illegal
(wired-OR)
Reset
Funnel
RST
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