F272-BAGE-T-TR STMicroelectronics, F272-BAGE-T-TR Datasheet - Page 75
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F272-BAGE-T-TR
Manufacturer Part Number
F272-BAGE-T-TR
Description
MCU 16BIT 256K FLASH 144-TQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.F272-BAGE-T-TR.pdf
(182 pages)
Specifications of F272-BAGE-T-TR
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-TQFP, 144-VQFP
Data Bus Width
16 bit
Data Ram Size
20 KB
Interface Type
ASC, CAN, I2C, SSC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
111
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 24 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
F272-BAGE-T-TR
Manufacturer:
STMicroelectronics
Quantity:
10 000
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ST10F272B/ST10F272E
16
I2C interface
The integrated I
two-line SDA/SCL in accordance with the I
operate in slave mode, in master mode or in multi-master mode. It can receive and transmit
data using 7-bit or 10-bit addressing. Data can be transferred at speeds up to 400 Kbit/s
(both Standard and Fast I
The module can generate three different types of interrupt:
●
●
●
These requests are issued to the interrupt controller by three different lines, and identified as
Error, Transmit, and Receive interrupt lines.
When the I
P4.7 (where SCL and SDA are respectively mapped as alternate functions) are
automatically configured as bidirectional open-drain: the value of the external pull-up
resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin
configuration.
When the I
controlled by P4, DP4 and ODP4.
The speed of the I
Fast I
Requests related to bus events, like start or stop events, arbitration lost, etc.
Requests related to data transmission
Requests related to data reception
2
C mode (100 to 400 kHz).
2
2
C module is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and
C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/ O
2
C Bus Module handles the transmission and reception of frames over the
2
C interface may be selected between Standard mode (0 to 100 kHz) and
2
C bus modes are supported).
2
C Bus specification. The I
2
C Module can
I2C interface
75/182
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