STR911FAW47X6 STMicroelectronics, STR911FAW47X6 Datasheet - Page 56

• Manufacturer Part Number: STR911FAW47X6
• Description: MCU ARM9 2048KB FLASH 128LQFP
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR911FAW47X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 2MB (2M x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• Processor Series: STR911x
• Core: ARM966E-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: CAN, SPI, UART
• Maximum Clock Frequency: 96 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory mapping
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If the main Flash contents are incorrect, the CPU, while executing code from the secondary
Flash, can download new data from any STR91xFA communication channel and program
into primary Flash memory. Application code then starts after the new contents of primary
Flash are verified.
STR91xFA memory map
The memory map is shown in
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●
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Either of the two Flash memories may be placed at CPU boot address 0x0000.0000.
By default, the primary Flash memory is in boot position starting at CPU address
0x0000.0000 and the secondary Flash memory may be placed at a higher address
following the end of the primary Flash memory. This default option may be changed
using the STR91xx device configuration software, placing the secondary Flash memory
at CPU boot location 0x0000.0000, and then the primary Flash memory may be placed
at a higher address.
The local SRAM (64KB or 96KB) is aliased in three address windows. A) At
0x0400.0000 the SRAM is accessible through the CPU’s D-TCM, at 0x4000.0000 the
SRAM is accessible through the CPU’s AHB in buffered accesses, and at 0x5000.0000
the SRAM is accessible through the CPU’s AHB in non-buffered accesses. An AHB bus
master other than the CPU can access SRAM in all three aliased windows, but these
accesses are always non-buffered. The CPU is the only AHB master that can
performed buffered writes.
APB peripherals reside in two AHB-to-APB peripheral bridge address windows, APB0
and APB1. These peripherals are accessible with buffered AHB access if the CPU
addresses them in the address range of 0x4800.0000 to 0x4FFF.FFFF, and non-
buffered access in the address range of 0x5800.0000 to 0x5FFF.FFFF.
Individual peripherals on the APB are accessed at the listed address offset plus the
base address of the appropriate AHB-to-APB bridge.
Figure 9: STR91xFA memory map on page
Doc ID 13495 Rev 6
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STR91xFAxxx