ST92F150CV9TB STMicroelectronics, ST92F150CV9TB Datasheet - Page 323
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ST92F150CV9TB
Manufacturer Part Number
ST92F150CV9TB
Description
IC MCU 8BIT CAN 64K MEM 100-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CV9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CV9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST92F150CV9TBE
Manufacturer:
ST
Quantity:
20 000
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J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)
These registers are structured in eight groups of
four registers. The user can gain access to these
registers programming the RSEL[2:0] bits of the
OPTIONS register while the RSEL[3] bit of the
same register must be placed at 1. In this way the
user can select the group where the registers that
he/she wants to use are placed. See the descrip-
tion of OPTIONS register for the correspondence
between registers and the values of RSEL[2:0] bits
(See
From the functional point of view, the FREG[0]-
FREG[31] registers can be seen as an array of
256 bits involved in the J1850 received message
filtering system.
The first byte received in a frame (following a valid
received SOF character) is an Identifier (I.D.) byte.
It is used by the JBLPD peripheral as the address
of the 256 bits array.
If the bit of the array correspondent to the I.D. byte
is set, then the byte is transferred to the RXDATA
Table
62).
J1850 Byte Level Protocol Decoder (JBLPD)
register and the RDRF flag is set. Also, every other
data byte received in this frame is transferred to
the RXDATA register unless the JBLPD peripheral
is put into sleep mode setting the SLP bit.
If the bit of the array correspondent to the I.D. byte
is clear, then the transfer of this byte as well as any
byte for the balance of this frame is inhibited, and
the RDRF bit remains cleared.
The bit 0 of the FREG[0] register (FREG[0].0 -
marked as F_00 in the previous table) corre-
sponds to the I.D. byte equal to 00h while the bit 7
of the FREG[31] register (FREG[31].7 - marked as
F_FF in the previous table) corresponds to the I.D.
byte equal to FFh.
Note: The FREG registers are undefined upon re-
set. Because of this, it is strongly recommended
that the contents of these registers has to be de-
fined before JE is set for the first time after reset.
Otherwise, unpredictable results may occur.
323/429
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