ST92F150CV9TB STMicroelectronics, ST92F150CV9TB Datasheet - Page 223
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ST92F150CV9TB
Manufacturer Part Number
ST92F150CV9TB
Description
IC MCU 8BIT CAN 64K MEM 100-LQFP
Manufacturer
STMicroelectronics
Series
ST9r
Datasheet
1.ST92F150CV1TB.pdf
(429 pages)
Specifications of ST92F150CV9TB
Core Processor
ST9
Core Size
8/16-Bit
Speed
24MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
77
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Processor Series
ST92F15x
Core
ST9
Data Bus Width
8 bit, 16 bit
Data Ram Size
2 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
24 MHz
Number Of Programmable I/os
80
Number Of Timers
16 bit
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST92F150-EPB
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST92F150CV9TB
Manufacturer:
STMicroelectronics
Quantity:
10 000
Part Number:
ST92F150CV9TBE
Manufacturer:
ST
Quantity:
20 000
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MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.5.10 Interrupts and DMA
10.5.10.1 Interrupts
The SCI can generate interrupts as a result of sev-
eral conditions. Receiver interrupts include data
pending, receive errors (overrun, framing and par-
ity), as well as address or break pending. Trans-
mitter interrupts are software selectable for either
Transmit Buffer Register Empty (BSN set) or for
Transmit Shift Register Empty (BSN reset) condi-
tions.
Typical usage of the Interrupts generated by the
SCI peripheral are illustrated in
The SCI peripheral is able to generate interrupt re-
quests as a result of a number of events, several
of which share the same interrupt vector. It is
therefore necessary to poll S_ISR, the Interrupt
Status Register, in order to determine the active
MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)
Figure
116.
trigger. These bits should be reset by the program-
mer during the Interrupt Service routine.
The four major levels of interrupt are encoded in
hardware to provide two bits of the interrupt vector
register, allowing the position of the block of point-
er vectors to be resolved to an 8 byte block size.
The SCI interrupts have an internal priority struc-
ture in order to resolve simultaneous events. Refer
also to Section 10.5.4 SCI-M Operating Modes for
more details relating to Synchronous mode.
Table 47. SCI Interrupt Internal Priority
Receive DMA Request
Transmit DMA Request
Receive Interrupt
Transmit Interrupt
Highest Priority
Lowest Priority
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