ST10R272LT6 STMicroelectronics, ST10R272LT6 Datasheet - Page 16

• Manufacturer Part Number: ST10R272LT6
• Description: IC MCU 16BIT LV ROMLESS 100-TQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10R272LT6

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SSP, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 77
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Processor Series: ST10R2x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 1 KB
• Interface Type: SSP, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 77
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: In Transition
• Other names: 497-2045

ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
5.2
Instruction pipelining
All MAC instructions use the 4-stage pipeline. During each stage the following tasks are
performed:
•
•
•
•
Note
Address generation
MAC instructions can use some standard ST10 addressing modes such as GPR direct or
#data4 for immediate shift value.
New addressing modes have been added to supply the MAC with two new operands per
instruction cycle. These allow indirect addressing with address pointer post-modification.
Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset
registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDX
pointer allows access to the entire memory space, but IDX
Port RAM, except for the CoMOV instruction.
16/77
1
FETCH: All new instructions are double-word instructions.
DECODE: If required, operand addresses are calculated and the resulting operands are
fetched. IDX and GPR pointers are post-modified if necessary.
EXECUTE: Performs the MAC operation. At the end of the cycle, the Accumulator and the
MAC condition flags are updated if required. Modified GPR pointers are written-back
during this stage, if required.
WRITEBACK: Operand write-back in the case of parallel data move.
MAC Operation
At least one instruction which does not use the MAC must be inserted between two
instructions that read from a MAC register. This is because the Accumulator and the
status of the MAC are modified during the Execute stage. The CoSTORE instruction
has been added to allow access to the MAC registers immediately after a MAC
operation.
i
are limited to the internal Dual-
i
). The GPR