ST72F361J9T6 STMicroelectronics, ST72F361J9T6 Datasheet - Page 99

• Manufacturer Part Number: ST72F361J9T6
• Description: IC MCU 8BIT 60K FLASH 44-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F361J9T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F36X-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

8-BIT TIMER (Cont’d)
10.5.3.4 One Pulse Mode
One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.
The one pulse mode uses the Input Capture1
function and the Output Compare1 function.
Procedure:
To use one pulse mode:
1. Load the OC1R register with the value corre-
2. Select the following in the CR1 register:
3. Select the following in the CR2 register:
Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FCh and OLVL2 bit is loaded on
the OCMP1 pin, the ICF1 bit is set and the value
FFFDh is loaded in the IC1R register.
Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.
sponding to the length of the pulse (see the for-
mula in the opposite column).
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Select the edge of the active transition on the
– Set the OC1E bit, the OCMP1 pin is then ded-
– Set the OPM bit.
– Select the timer clock CC[1:0] (see
plied to the OCMP1 pin after the pulse.
plied to the OCMP1 pin during the pulse.
ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).
icated to the Output Compare 1 function.
Clock Control
event occurs
on ICAP1
Counter
= OC1R
When
When
Bits).
One pulse mode cycle
OCMP1 = OLVL2
OCMP1 = OLVL1
ICR1 = Counter
Counter is reset
ICF1 bit is set
to FCh
Table 19
Clearing the Input Capture interrupt request (that
is, clearing the ICFi bit) is done in two steps:
1. Reading the SR register while the ICFi bit is set.
2. An access (read or write) to the ICiLR register.
The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:
Where:
t
f
PRESC
When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See
Notes:
1. The OCF1 bit cannot be set by hardware in one
2. When the Pulse Width Modulation (PWM) and
3. If OLVL1=OLVL2 a continuous signal will be
4. The ICAP1 pin can not be used to perform input
5. When one pulse mode is used OC1R is dedi-
CPU
pulse mode but the OCF2 bit can generate an
Output Compare interrupt.
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
seen on the OCMP1 pin.
capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.
cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.
= Pulse period (in seconds)
= PLL output x2 clock frequency in hertz
= Timer prescaler factor (2, 4, 8 or 8000
OCiR Value =
(or f
depending on the CC[1:0] bits, see
ble 19 Clock Control
OSC
/2 if PLL is not enabled)
PRESC
t
*
f
CPU
Bits)
- 5
Figure
ST72361
99/225
68).
Ta-