Z8F0422PJ020EG Zilog, Z8F0422PJ020EG Datasheet - Page 134

• Manufacturer Part Number: Z8F0422PJ020EG
• Description: IC ENCORE MCU FLASH 4K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0422PJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z8F042xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4140; Z8F0422PJ020EG

Table 63. SPI Data Register (SPIDATA)
SPI Control Register Definitions
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
SPI Data Register
7
The SPI Data Register stores both the outgoing (transmit) data and the incoming (receive)
data. Reads from the SPI Data Register always return the current contents of the 8-bit
Shift Register. Data is shifted out starting with bit 7. The last bit received resides in bit
position 0.
With the SPI configured as a Master, writing a data byte to this register initiates the data
transmission. With the SPI configured as a Slave, writing a data byte to this register loads
the shift register in preparation for the next data transfer with the external Master. In either
the Master or Slave modes, if a transmission is already in progress, writes to this register
are ignored and the Overrun error Flag, OVR, is set in the SPI Status Register.
When the character length is less than 8 bits (as set by the NUMBITS field in the SPI Mode
Register), the transmit character must be left justified in the SPI Data Register. A received
character of less than 8 bits is right justified (last bit received is in bit position 0). For
example, if the SPI is configured for 4-bit characters, the transmit characters must be
written to SPIDATA[7:4] and the received characters are read from SPIDATA[3:0].
DATA—Data
Transmit and/or receive data.
6
5
4
DATA
F60H
R/W
X
3
Z8 Encore! XP
2
Product Specification
Serial Peripheral Interface
1
®
F0822 Series
0
121