ST7FLITE25F1B6 STMicroelectronics, ST7FLITE25F1B6 Datasheet - Page 173
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ST7FLITE25F1B6
Manufacturer Part Number
ST7FLITE25F1B6
Description
IC MCU 8BIT 8K FLASH 20-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST7FLITE25F1B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE2x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Table 117. LART_PWM_Mode
Notes:
– This function can be used only with ST7FLite0 devices.
– This function is used to keep backward compatibility with previous library. For new develop-
Function Name
Function Prototype
Behaviour Description
Input Parameter 1
Input Parameter 2
Input Parameter 3
Output Parameters
Required Preconditions
Functions called
Postconditions
See also
ment LART_ConfigurePWM function should be used with the first parameter LART_PWM0
in place of this function.
LART_PWM_Mode
Void LART_PWM_Mode(unsigned int
Autoreload_Value,Lart_Output POLARITY, unsigned int
Dutycycle_Data)
Generates PWM on PWM0 pin. The PWM signal frequen-
cy is controlled by the counter clock period and ATR reg-
ister value. The PWM signal duty cycle depends upon
input parameter 1 and input parameter 3.
This function is used only for Lite0 device, for other devic-
es use LART_ConfigurePWM.
Autoreload_Value
This value is loaded in autoreload register (ATR). You can
select this value from 0x000 to 0xFFF depending on the
frequency required for the PWM signal.
LART_POLARITY_0
PWM output level is low, for Counter value >
Dutycycle_Data,
PWM output level is high, for Counter value <=
Dutycycle_Data.
LART_POLARITY_1
PWM output level is high, for Counter value >
Dutycycle_Data,
PWM output level is low, for Counter value <=
Dutycycle_Data.
Dutycycle_Data
Data to be loaded in Duty cycle register (0x000 to 0xFFF).
Note: This value must be greater than the ATR register
value loaded through Input parameter 1 to obtain signal on
PWM0 pin.
None
LART_Init must have been called to select the counter
clock.
None
PWM signal of required frequency and duty cycle is gen-
erated at PWM0 pin. The output compare mode is disa-
bled.
LART_Init, LART_ConfigurePWM
Function Descriptions
173/235
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