ST7FLITE35F2B6 STMicroelectronics, ST7FLITE35F2B6 Datasheet - Page 98
![IC MCU 8BIT 8K FLASH 20DIP](/photos/6/89/68911/497-20-dip__300_mil__narrow_pdip_mdip__series_sml.jpg)
ST7FLITE35F2B6
Manufacturer Part Number
ST7FLITE35F2B6
Description
IC MCU 8BIT 8K FLASH 20DIP
Manufacturer
STMicroelectronics
Series
ST7r
Specifications of ST7FLITE35F2B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ST7FLITE3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
384 B
Interface Type
LINSCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
15
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Development Tools By Supplier
ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5085 - EVAL BOARD UNIV MOTOR CONTROL497-5049 - KIT STARTER RAISONANCE ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
ST7LITE3xF2
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
11.5.5.6 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non-addressed receivers.
The non-addressed devices may be placed in
sleep mode by means of the muting function.
Setting the RWU bit by software puts the SCI in
sleep mode:
All the reception status bits can not be set.
All the receive interrupts are inhibited.
A muted receiver may be woken up in one of the
following ways:
– by Idle Line detection if the WAKE bit is reset,
– by Address Mark detection if the WAKE bit is set.
Idle Line Detection
Receiver wakes up by Idle Line detection when the
Receive line has recognized an Idle Line. Then the
RWU bit is reset by hardware but the IDLE bit is
not set.
This feature is useful in a multiprocessor system
when the first characters of the message deter-
mine the address and when each message ends
by an idle line: As soon as the line becomes idle,
every receivers is waken up and analyse the first
characters of the message which indicates the ad-
dressed receiver. The receivers which are not ad-
dressed set RWU bit to enter in mute mode. Con-
sequently, they will not treat the next characters
constituting the next part of the message. At the
end of the message, an idle line is sent by the
transmitter: this wakes up every receivers which
are ready to analyse the addressing characters of
the new message.
In such a system, the inter-characters space must
be smaller than the idle time.
Address Mark Detection
Receiver wakes up by Address Mark detection
when it received a “1” as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.
This feature is useful in a multiprocessor system
when the most significant bit of each character
(except for the break character) is reserved for Ad-
dress Detection. As soon as the receivers re-
98/173
1
ceived an address character (most significant bit
= ’1’), the receivers are waken up. The receivers
which are not addressed set RWU bit to enter in
mute mode. Consequently, they will not treat the
next characters constituting the next part of the
message.
11.5.5.7 Parity Control
Hardware byte Parity control (generation of parity
bit in transmission and parity checking in recep-
tion) can be enabled by setting the PCE bit in the
SCICR1 register. Depending on the character for-
mat defined by the M bit, the possible SCI charac-
ter formats are as listed in
Note: In case of wake-up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Table 20. Character Formats
Legend: SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Even parity: The parity bit is calculated to obtain
an even number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain
an odd number of “1s” inside the character made
of the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit
will be 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS = 0) or an odd number of “1s” if odd parity is
selected (PS = 1). If the parity check fails, the PE
flag is set in the SCISR register and an interrupt is
generated if PCIE is set in the SCICR1 register.
M bit
0
1
PCE bit
1
0
0
1
| SB | 7-bit data | PB | STB |
| SB | 8-bit data | PB | STB |
| SB | 8 bit data | STB |
| SB | 9-bit data | STB |
Character format
Table
20.