Z8F0412SJ020SG Zilog, Z8F0412SJ020SG Datasheet - Page 136

• Manufacturer Part Number: Z8F0412SJ020SG
• Description: IC ENCORE MCU FLASH 4K 28SOIC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0412SJ020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: Z8F041xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4107; Z8F0412SJ020SG

Table 65. SPI Status Register (SPISTAT)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
R/W* = Read access. Write a 1 to clear the bit to 0.
SPI Status Register
IRQ
7
The SPI Status Register indicates the current state of the SPI. All bits revert to their reset
state if the
IRQ—Interrupt Request
If SPIEN = 1, this bit is set if the STR bit in the SPICTL Register is set, or upon comple-
tion of an SPI Master or Slave transaction. This bit does not set if SPIEN = 0 and the SPI
Baud Rate Generator is used as a timer to generate the SPI interrupt.
0 = No SPI interrupt request pending.
1 = SPI interrupt request is pending.
OVR—Overrun
0 = An overrun error has not occurred.
1 = An overrun error has been detected.
COL—Collision
0 = A multi-master collision (mode fault) has not occurred.
1 = A multi-master collision (mode fault) has been detected.
ABT—SLAVE mode transaction abort
This bit is set if the SPI is configured in SLAVE mode, a transaction is occurring and SS
deasserts before all bits of a character have been transferred as defined by the NUMBITS
field of the SPIMODE Register. The IRQ bit also sets, indicating the transaction has
completed.
0 = A SLAVE mode transaction abort has not occurred.
1 = A SLAVE mode transaction abort has been detected.
Reserved—Must be 0
TXST—Transmit Status
0 = No data transmission currently in progress.
1 = Data transmission currently in progress.
SLAS—Slave Select
If SPI enabled as a Slave
0 = SS input pin is asserted (Low)
1 = SS input is not asserted (High).
If SPI enabled as a Master, this bit is not applicable.
OVR
SPIEN
6
R/W*
bit in the SPICTL Register equals 0.
COL
5
ABT
4
0
F62H
3
Reserved
Z8 Encore! XP
2
Product Specification
R
Serial Peripheral Interface
TXST
1
®
F0822 Series
SLAS
0
1
123