ST7FLITE05M6TR STMicroelectronics, ST7FLITE05M6TR Datasheet - Page 48
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ST7FLITE05M6TR
Manufacturer Part Number
ST7FLITE05M6TR
Description
IC MCU 8BIT FLASH 16SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.ST7FLITES2Y0B6.pdf
(124 pages)
Specifications of ST7FLITE05M6TR
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
PWM, WDT
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Processor Series
ST7FLITE0x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
ST7LITE0xY0, ST7LITESxY0
11 ON-CHIP PERIPHERALS
11.1 LITE TIMER (LT)
11.1.1 Introduction
The Lite Timer can be used for general-purpose
timing functions. It is based on a free-running 8-bit
upcounter with two software-selectable timebase
periods, an 8-bit input capture register and watch-
dog function.
11.1.2 Main Features
■
■
Figure 31. Lite Timer Block Diagram
48/124
1
LTIC
Realtime Clock
– 8-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz f
– Maskable timebase interrupt
Input Capture
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
f
OSC
/32
LTICR
8-bit UPCOUNTER
INPUT CAPTURE
REGISTER
8-bit
8
7
LTCSR
ICIE
f
f
LTIMER
LTIMER
/2
ICF
OSC
TB
)
1
0
f
To 12-bit AT TImer
WDG
Timebase
1 or 2 ms
(@ 8 MHz
f
OSC
TBIE
■
)
– Enabled by hardware or software (configura-
– Optional reset on HALT instruction (configura-
– Automatically resets the device unless disable
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
Watchdog
ble by option byte)
ble by option byte)
bit is refreshed
TBF
WDG
RF
WATCHDOG
LTIC INTERRUPT REQUEST
LTTB INTERRUPT REQUEST
WDGE
WDGD
0
WATCHDOG RESET