EP9307-IRZ Cirrus Logic Inc, EP9307-IRZ Datasheet - Page 4

IC ARM9 SOC ARM920T 272TFBGA

EP9307-IRZ

Manufacturer Part Number
EP9307-IRZ
Description
IC ARM9 SOC ARM920T 272TFBGA
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9307-IRZ

Core Size
16/32-Bit
Core Processor
ARM9
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
272-TFBGA
Controller Family/series
(ARM9)
No. Of I/o's
14
Ram Memory Size
32MB
Cpu Speed
200MHz
No. Of Timers
3
No. Of Pwm Channels
1
Digital Ic Case Style
TFBGA
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9307A-Z
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1133 - KIT DEVELOPMENT EP9307 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1256

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP9307-IRZ
Manufacturer:
CIRRUS
Quantity:
3 468
Part Number:
EP9307-IRZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
EP9307-IRZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
RTC
4
Raster
EP9312 User's Guide Update
As designed, horizontal clock and data are not aligned. Where horizontal clock gating is required, set
HACTIVESTRTSTOP equal to HCLKSTRTSTOP+5.
Description 1
If the raster engine is using single scan mode, two and two thirds per pixel mode (3 bits per pixel over an 8-
bit bus) works correctly. If the raster engine is programmed to use two and two thirds pixels per clock shift
mode with dual scan enabled, it will not generate valid timings for dual scan displays.
Workaround
There is no known workaround at this time.
Description 2
YCrCb formatted video will not produce the valid synchronization signals in 656 video mode.
Workaround
Design the system with an NTSC/PAL DAC that accepts RGB input signals.
Description
The internal RTC oscillator is susceptible to noise which can lead to extra clocks on the internal 32.768-kHz
signal.
Workaround
Please refer to application note AN265, “EP93xx RTC Oscillator Circuit”, which can be found at
http://www.cirrus.com/en/pubs/appNote/AN265REV2.pdf
No fix of this bug is planned for future silicon revisions.
ER667E2B

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