LPC3141FET180,551 NXP Semiconductors, LPC3141FET180,551 Datasheet - Page 15

• Manufacturer Part Number: LPC3141FET180,551
• Description: IC ARM9 MCU USB OTG 180TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3141FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 270MHz
• Connectivity: EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Number Of I /o: 20
• Program Memory Type: ROMless
• Ram Size: 192K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJS
• Data Bus Width: 32 bit
• Data Ram Size: 192 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 270 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 1.2 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: OM11037
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935289711551

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.4 NAND flash controller
The NAND flash controller is used as a dedicated interface to NAND flash devices.
Figure 4
module is formed by a controller block that controls the flow of data from/to the AHB bus
through the NAND flash controller block to/from the (external) NAND flash. An Error
Correction Code (ECC) module allows for hardware error correction for support of
Multi-Level Cell (MLC) NAND flash devices. The NAND flash controller is connected to
the AES block to support secure (encrypted) code execution (see
Before data is written from the buffer to the NAND flash, optionally it is first protected by
an error correction code generated by the ECC module. After data is read from the NAND
flash, the error correction module corrects errors, and/or the AES decryption module can
decrypt data.
This module has the following features:
Fig 4. Block diagram of the NAND flash controller
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ARM926 debug access
Boundary scan
The ARM926 debug access can be permanently disabled through JTAG security bits
in the One-Time Programmable memory (OTP) block.
Dedicated NAND flash interface with hardware controlled read and write accesses.
Wear leveling support with 516-byte mode.
Software controlled command and address transfers to support wide range of flash
devices.
Software control mode where the ARM is directly master of the flash device.
(1) AES decoder available on LPC3143 only.
shows a block diagram of the NAND flash controller module. The heart of the
All information provided in this document is subject to legal disclaimers.
Rev. 0.16 — 27 May 2010
DECODER
AHB MULTI-LAYER MATRIX
AES
NAND INTERFACE
CONTROLLER
(1)
BUFFER
ENCODER/
DECODER
ECC
DMA transfer request
LPC3141/3143
002aae083
Section
© NXP B.V. 2010. All rights reserved.
6.21).
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