LPC1111FHN33/101,5 NXP Semiconductors, LPC1111FHN33/101,5 Datasheet - Page 30
![IC MCU 32BIT 8KB FLASH 33HVQFN](/photos/6/51/65170/568-32-hvqfn_sml.jpg)
LPC1111FHN33/101,5
Manufacturer Part Number
LPC1111FHN33/101,5
Description
IC MCU 32BIT 8KB FLASH 33HVQFN
Manufacturer
NXP Semiconductors
Series
LPC1100r
Datasheets
1.LPC1114FHN333015.pdf
(2 pages)
2.LPC1114FHN333015.pdf
(66 pages)
3.LPC1114FHN333015.pdf
(66 pages)
Specifications of LPC1111FHN33/101,5
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
33-VQFN Exposed Pad, 33-HVQFN, 33-SQFN, 33-DHVQFN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
28
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC11
Core
ARM Cortex M0
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
28
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
33HVQFN EP
Device Core
ARM Cortex M0
Family Name
LPC1100
Maximum Speed
50 MHz
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
622-1005 - USB IN-CIRCUIT PROG ARM7 LPC2K
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4957
935290771551
935290771551
NXP Semiconductors
LPC1111_12_13_14
Product data sheet
CAUTION
7.16.5 APB interface
7.16.6 AHBLite
7.16.7 External interrupt inputs
7.17 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC111x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
All GPIO pins can be level or edge sensitive interrupt inputs. In addition, start logic inputs
serve as external interrupts (see
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug with four
breakpoints and two watchpoints is supported.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the UART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 10 February 2011
Section
7.16.1).
32-bit ARM Cortex-M0 microcontroller
LPC1111/12/13/14
© NXP B.V. 2011. All rights reserved.
30 of 66